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The Austin, TX-based industry research consortium SEMATECH says that the high electron mobilities of III-V compounds make them prime candidates for future NMOS channel materials. Specifically, indium gallium arsenide (InGaAs) is likely to be the material of choice, according to the consensus of more than 60 industry and university researchers in the invitational workshop ‘III-V CMOS on Si: Technical and Manufacturing Needs’ at last week’s IEEE International Electron Devices Meeting (IEDM) in Washington DC, USA (organized by SEMATECH and sponsored by deposition equipment maker Aixtron AG of Aachen, Germany).

InGaAs, with a mobility performance of 6-10 times that of silicon (Si), has emerged as a leading candidate channel material in dual-channel devices that may consist of germanium-based PMOS and III-V-based NMOS field-effect transistors (FETs), with proponents of III-V expressing optimism over the manufacturability.

However, in the workshop several delegates expressed concern that such materials-based solutions for performance enhancement could not be brought to manufacturing in time, and that many issues that need to be addressed to realize performance improvement would not be resolved in time for use in devices at the 22nm technology node and beyond.

According to SEMATECH, technologists also agreed that inserting III-V materials on Si devices poses several challenges, including lattice mismatch, poor interface quality, high-k dielectric growth and off-state current leakage. However, the scalability of metal-organic chemical vapor deposition (MOCVD) attracted a consensus as the most promising manufacturing process, with clustered chambers for III-V and high-k suggested as an effective tool configuration for increased throughput. Opening speaker Robert Chau of Intel urged researchers to collaborate on resolving these and other issues. “By 2012, we should have a real working solution for III-V,” he believes.

*In the IEDM technical sessions that followed, engineers from SEMATECH’s Front End Processes (FEP) Division presented five papers detailing progress in developing a manufacturable high-k metal gate-stack solution for advanced 32-22nm device technology generations, including the use of flash annealing, a new gate stack material for scaling EOT (equivalent oxide thickness) down to 0.85nm, and new possibilities for performance improvement through use of alternate orientation Si surfaces and strained SiGe and Ge channels.

In ‘Impact of Flash Annealing on Performance and Reliability of High-k/Metal-Gate MOSFETs for sub-45nm CMOS’, lead author Pankaj Kalra reported the successful use of millisecond annealing on scaled high-k metal gated devices to form ultra-shallow junctions that meet requirements for sub-45nmn CMOS technology.

Wafers were ramped up to an intermediate temperature followed by using flash lamps to heat the device side of the wafer to the peak anneal temperature of 1300°C. Subsequent testing revealed that, unlike spike annealing, dopant diffusion (which causes excessive junction depths) is minimized and dopant activation is actually improved.

Also, the process does not significantly affect bulk charge trapping (one of the major performance/reliability issues in high-k dielectrics). The flash process can achieve junction depths of about 12-15nm with low effective sheet resistance (meeting 32nm technology targets).

In another paper, lead author Rusty Harris reported that high-k/metal gates on NMOS FETs fabricated on the 110 silicon crystal plane demonstrate respectable output performance due to velocity saturation of electrons. “High-k seems to be an important element in making the 110 channel very realistic,” Harris notes.

Also, it appears that off-state current can be controlled in Si(110) in the same way as the more conventional Si(100) orientation, allowing Si(110) NMOS and PMOS structures to be used effectively in low-standby-power (LTSP) devices. So, Si(110) may provide a significant improvement for high-performance (HP) and LTSP devices without the process complexity typical of mixed-orientation CMOS approaches.

A paper presented by lead author Sagar Suthram discussed silicon-germanium with strained quantum wells (QWs), which could offer a replacement for silicon channels for 22nm and beyond, meeting future low-power and high-performance requirements that are probably too great for silicon-based materials. These QW devices – which use the quantum well effect of confining charge carriers to a two-dimensional plane, improving their transport characteristics – exhibit a low band-to-band tunneling current and provide significant mobility enhancements. The QW devices display a strain response similar to that of Si, indicating that scaling pathways with Ge-based devices exist.

In two more papers, SEMATECH engineers also released new details on enabling approaches for dual metal gate technology:

Enriching high-k materials with oxygen in a low-temperature process is an effective way to diminish flat-band roll-off (Vfb), which is the main challenge to achieving low PMOS threshold voltage (Vt) and thin EOT simultaneously. Lead author S.C. Song et al discovered that progressive oxygen vacancy generation causes Vfb roll-off, shedding light on a little-understood phenomenon.

Also, Prasanna Sivasubramani et al have demonstrated a second-generation higher-k gate stack material, hafnium titanium silicon oxynitride (HfTiSiON), as an effective successor to first-generation HfSiON gate dielectric materials. With an aggressively scaled dielectric constant (k) of about 40, and low leakage, HfTiSiON appears to answer gate stack manufacturability needs for the 32nm generation and beyond. “For the first time, we addressed the thermodynamic instability of TiO2-containing dielectrics,” says lead author Sivasubramani. “This may enable gate stack scaling beyond HfO2,” he concludes.

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