News: Microelectronics
15 December 2021
Intel unveils packaging, transistor and quantum physics developments to sustain Moore’s Law beyond 2025
In its pursuit of Moore’s Law, Intel has unveiled key packaging, transistor and quantum physics breakthroughs that it says are fundamental to advancing and accelerating computing well into the next decade. At the 67th Annual IEEE International Electron Devices Meeting (IEDM 2021), Intel outlined its path toward more than 10x interconnect density improvement in packaging with hybrid bonding, 30-50% area improvement in transistor scaling, major breakthroughs in new power and memory technologies, and new concepts in physics that could revolutionize computing, the firm reckons.
“Our Components Research Group is sharing key research breakthroughs at IEDM 2021 in bringing revolutionary process and packaging technologies to meet the insatiable demand for powerful computing,” says Robert Chau, Intel senior fellow & general manager of Components Research.
Moore’s Law has been tracking innovations in computing that meet the demands of every technology generation from mainframes to mobile phones. This evolution continues as we move into a new era of computing with unlimited data and artificial intelligence (AI), says Intel.
Intel’s Components Research Group is innovating across three key areas: essential scaling technologies for delivering more transistors; new silicon capabilities for power and memory gains; and exploration of new concepts in physics to revolutionize the way the world does computing. Many of the innovations that broke through previous barriers of Moore’s Law and are in today’s products started with the work of Component Research – including strained silicon, Hi-K metal gates, FinFET transistors, RibbonFET, and packaging innovations including EMIB and Foveros Direct.
Intel says that, at IEDM 2021, it is demonstrating that it is on track to continue the advancement and benefits of Moore’s Law well beyond 2025 through three areas of pathfinding.
1. Intel is pursuing research in essential scaling technologies for delivering more transistors in future product offerings:
- Researchers have outlined solutions for the design, process and assembly challenges of hybrid bonding interconnect, envisioning a more than 10x interconnect density improvement in packaging. At the Intel Accelerated event in July, the firm announced plans to introduce Foveros Direct, enabling sub-10-micron bump pitches, providing an order-of-magnitude increase in the interconnect density for 3D stacking. To enable the ecosystem to gain benefits of advanced packaging, Intel is also calling for the establishment of new industry standards and testing procedures to enable a hybrid bonding chiplet ecosystem.
- Looking beyond its gate-all-around (GAA) RibbonFET, Intel is tackling the coming post-FinFET era with an approach to stacking multiple (CMOS) transistors that aims to achieve a maximized 30-50% logic scaling improvement for the continued advancement of Moore’s Law by fitting more transistors per square millimeter.
- Intel is also paving the way for Moore’s Law advancement into the angstrom era with research showing how novel materials just a few atoms thick can be used to make transistors that overcome the limitations of conventional silicon channels, enabling millions more transistors per die area for ever more powerful computing in the next decade.
2. Intel is bringing new capabilities to silicon:
- More efficient power technologies are advancing through the world’s first integration of gallium nitride (GaN)-based power switches with silicon-based CMOS on a 300mm wafer. This sets the stage for low-loss, high-speed power delivery to CPUs while simultaneously reducing motherboard components and space.
- Another advancement is Intel’s low-latency read/write capabilities using novel ferroelectric materials for possible next-generation embedded DRAM technology that can deliver greater memory resources to address the growing complexity of compute applications, from gaming to AI.
3. Intel is pursuing massive performance with silicon transistor-based quantum computing, as well as entirely new switches for massively energy-efficient computing with novel room-temperature devices. In the future, these developments may replace classic MOSFET transistors by using entirely new concepts in physics:
- At IEDM, Intel demonstrated what is claimed to be the first experimental realization of a magnetoelectric spin-orbit (MESO) logic device at room temperature, showing the potential manufacturability for a new type of transistor based on switching nanoscale magnets.
- Intel and nanoelectronics research center IMEC of Leuven, Belgium are making progress with spintronic materials research to take device integration research close to realizing a fully functional spin-torque device.
- Intel also showcased full 300mm qubit process flows for the realization of scalable quantum computing that is compatible with CMOS manufacturing and identifies the next steps for future research.
