News: Optoelectronics
24 September 2020
CompoundTek’s wafer edge coupling targets SiPh commercialization from Q1/2021
Singapore-based silicon photonic (SiPh) foundry services provider CompoundTek Pte Ltd has confirmed its development for a 8”/12” agnostic silicon photonics wafer test hub. Expansion will be centred on addressing two key areas of market demand: wafer-level edge coupling capability and test time reduction for commercial product companies.
Silicon photonic wafer test is currently performed by vertical optical coupling of the light into the device under test (DUT), contrary to the actual end-application where light is coupled horizontally into the device through the coupler at the edge of the die. Creating a mismatch between the wafer test environment and final application often leads to potential gaps in SiPh test coverage, reinforcing the need for real-world-based test scenarios to screen out failures.
CompoundTek’s development of the new wafer edge coupling technologies aims to increase the coverage of existing SiPh wafer test by including the detection of fails due to edge couplers.
Scheduled to be offered to key customers from first-quarter 2021, the wafer-level edge coupling capability is being developed alongside expansion efforts of the firm’s Test Executive Systems (TES). Representing a key challenge to broader market SiPh adoption, long test time per wafer – varying from 36 hours to as long as 96 hours, depending on the test type needed and coverage – is unlike the well-established CMOS logic product supply chain.
Long test time is attributed to the complex opto-electrical (DC and RF) tests and, without a standardized SiPh wafer test solution capable of balancing test coverage with competitive test time, successful integration of optical components on a chip for SiPh devices is delayed, creating roadblocks to mass-market adoption of SiPh technologies.
CompoundTek says that recent breakthroughs via optimization of its proprietary TES executive can potentially reduce customers’ product test time by up to 40%, to as short as 1.5 hours (from 2.5 hours) or 70 hours (from 96 hours). Enabling large volumes of device-performance data necessary to carry a design from concept to qualification and subsequently into production, TES aims to accelerate market adoption of wafer-level SiPh test services.
Going beyond this, and to further improve test time, CompoundTek has also started work on strategies for test parallelism to drive down the cycle time of SiPh wafer test. Estimated to be completed in two years, TES is poised to improve test cycle time by an additional 40%, making it a likely candidate for the first-of-its-kind service that better integrates SiPh value chain and solidify the manufacturing ecosystem, it is reckoned.
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