News

17 February 2009

 

SRC and IMEC collaborate on environmentally friendly chip-making methods

University-research consortium Semiconductor Research Corp (SRC) of Research Triangle Park, NC, USA and nanoelectronics research center IMEC in Leuven, Belgium have agreed to establish an international collaboration aimed at creating novel processes and materials for advanced semiconductor manufacturing. The memorandum of understanding (MOU) calls for the consortia to apply their more than 50 years of combined expertise to finding more environmentally friendly chip manufacturing methods.

The effort will bring together SRC's university research for sustainable high-performance materials and processes with IMEC's expertise in research of deep-submicron IC process technologies and devices. The work will be conducted among IMEC and the joint SRC/SEMATECH Center for Environmentally Benign Semiconductor Manufacturing (CEBSM).

What was formerly the NSF/SRC Engineering Research Center (ERC) for Environmentally Benign Semiconductor Manufacturing (until 2006) was established in 1996 by SRC and the US National Science Foundation (NSF) as a university/industry consortium together with the University of Arizona, Massachusetts Institute of Technology, Stanford University, and the University of California-Berkeley (joined in 1998 by Cornell University, Arizona State University and MIT Lincoln Laboratory, and in 1999 by the University of Maryland). CEBSM’s expertise focuses on addressing strategic ESH-related research challenges.

The new IMEC-CEBSM collaboration’s cooperative work targets two objectives: creating leading-edge technologies that protect the environment, and more effective processes for lowering the costs of chip manufacturing.

SRC, IMEC, and CEBSM intend to start the first phase of the joint initiative with an emphasis in two areas.

The first area focuses on sustainable cleaning and surface preparation of new materials and nano-structures, including the timely integration of new channel and gate materials such as germanium (Ge) and III/V compounds. The research will establish options for minimizing emissions and decreasing the usage of chemicals (including deposition precursors, etch chemicals and cleaning agents), water and energy during processing. The joint initiative will also explore novel in-line and real-time approaches for monitoring the efficacy of nano-structure cleaning processes.

The second area aims to explore sustainable high-performance material planarization processes. This research will advance the design and feasibility of process options that eliminate the release and discharge of nanoparticles in the manufacturing waste streams.

“Semiconductors have made enormous progress in speed, performance, and miniaturization, which places greater demand on the environmental aspects required,” says SRC’s president & CEO Larry Sumney. “Joining the considerable talents of SRC and IMEC with the CEBSM’s proven track record for high-impact ESH research demonstrates the commitment of the chip industry to stewardship of the global environment,” he adds.

“By joining forces with CEBSM's experts, we will be able to complement our advanced semiconductor scaling research with ESH aspects already at a very early stage of researching new processes and materials for next-generation IC technologies,” says IMEC’s president & CEO Gilbert Declerck. “Such collaboration will offer our partners an added value towards future volume manufacturing.”

Further details of the R&D plans covered by the MOU will be presented at CEBSM’s annual meeting this week (19-20 February) at the University of Arizona in Tucson.

Search: SRC IMEC Channel and gate materials Germanium

Visit: www.src.org

Visit: www.imec.be